VHDL Modeling for Analog-Digital Hardware Designs
Balsha R. Stanisic, Mark Brown · 1989
Historically the analog and digital partitions of a hardware design have been modeled in different languages and simulated usir.g separate simulators. Each simulation has been adequate within its partition, but these partitions could not Le combined. Simulating the analog-digital interaction and assuring that it reflects the physical analog-digital interconnection is required to insure a good design. The VHSIC Hardware Description Language (VHDL) and its associated simulator can model and simulate the analog-digital interaction assuring that it reflects the analog-digital physical intexonnection because VHDL can describe both analog and digital circuits behaviorally and structurally. This paper describes techniques for simulation modeling and a physical design verification methodology for assuring simulation and interconnection correspondence. Following the introductory material, details of the simulation model are presented. Then a description of a physical design verification methodology is given, followed by results from current designs and finally, key points are summarized.