Low-power MPEG2 encoder architecture for digital CMOS camera
J.Y.F. Hsieh, T.H. Meng · 2002
A low-power, large-scale parallel MPEG2 encoder architecture for a single-chip digital CMOS video camera is discussed in this paper. This single-chip architecture includes a 640/spl times/480 array of CMOS photodiodes, each pixel with an 8-bit dynamic range per color plane, and embedded DRAM for storing 4 frames of data. The parallel processor architecture is designed to implement highly computationally intensive image and video processing tasks such as color conversion, DCT, and motion estimation for MPEG-2. When clocked at 40 MHz with two ALU pipeline stages, it delivers a processing performance of 1.6 billion operations per second (BOPS) and can support frame rates of up to 30 fps. The architecture is specifically designed for low power consumption. When implemented in a 0.2 micron CMOS technology at a 1.5 V supply voltage, it will consume 40 mW, thus providing a power efficiency of 40 BOPS/Watt.