A HIGH THROUGHPUT AND ERROR TOLERANT AES DESIGN
C. Thamilarasi, K. Shanmugapriya · 2013
The Advanced Encryption Standard (AES) has been lately accepted as the symmetric cryptography standard for confidential data transmission. The AES cipher is specified as a number of repetitions of transformation rounds that convert the input plain-text into the final output of cipher-text. All rounds consists of several processing steps including one that depends on the encryption key. A set of reverse rounds applied to transform cipher-text back into the original plain- text using the same encryption key. The proposed schemes are independent of the way the S-box and the inverse S-box are constructed. Therefore, they can be used for both S-boxes and the inverse S-boxes using lookup tables and those utilizing logic gates based on composite fields. Furthermore, for each composite field constructions, there exists eight possible isomorphic mapping. Therefore, after the exploitation of a new common subexpression elimination algorithm, the isomorphic mapping that result in the minimal implementation area cost is chosen. A high throughput hardware implementations of our proposed CFA AES S-boxes are reported. In order to avoid data corruption due to SEU's a novel fault tolerant model of AES is presented which is based on the Hamming error correction code. This reduces the data corruption and increase the performance.Thus the data corruption due to Single Event Upset can be avoided and the performance was increased.