Architectures of Fault-Tolerant Network Interfaces and Router For Network-On-Chip
Anusree S Anusree S · International Journal of Scientific Research · 2012
This paper introduces a Fault-Tolerant Network Interfaces and Router for Network on Chip. Networks- on-Chip which constitute the interconnection architecture for the complex designs, may undergo malfuctions and failures due to the technology scaling and complexity. This can be overcome by adopting a functional fault model for the com- ponents of the NI and Router in the Network on Chip.The proposed Fault-Tolerant solution can be used to mitigate both temporary and permanent faults in the NI. This paper proposing a new architecture to the NI components,FIFOs and Look Up Tables, which are most sensitive to faults.This architectural solution can also provide a saving of up to 48% in the area overhead, as well as a significant energy reduction, with respect to an alternative standard Triple Modular Redundancy implementation of the NI, while maintaining a similar level of robustness to faults.