Implementation of Reconfigurable Fault Tolerant Network on Chip for Aerospace Applications
A. Karthikeyan, Pankaj Kumar, Velusamy Parthasarathy · 2013
The reliability of the software chip is the essential factor in VLSI design since the chip can be implanted in any embedded circuit varies from simple adder to crucial satellite device. Thus breach in VLSI chip operation may results in huge negative impact devastation. A novel architecture of VLSI chip testing design is proposed and unlike from normal BIST structure this structure ensures the safety of entire aircraft by monitoring the flow of signals around aircraft and controlling various part of the system for better security. ERRIC architecture is initially proven to be best testing and controlling structure for aircraft applications. Performance analysis of area, power, and timing constraints has been proved better using Quartus - II synthesizer tool. A method of Nios Processor controlled aircraft safety is ensured as a new proposal. Nios processor design has the unique advantage of high accuracy and flexibility over reconfigurable Network on chip applications. (A. Karthikeyan, P. Senthil Kumar, V. Parthasarathy. Implementation of Reconfigurable Fault Tolerant Network on Chip for Aerospace Applications. Life Sci J 2013;10(2):2823-2835) (ISSN:1097-8135). http://www.lifesciencesite.com. 391