Low PowerMinimum Transistor Building Blocks for the Implementation of Back-Propagation Algorithms
Puebla Mexico · 1997
Several building blocks intended for on-chip learning neural networks are proposed. The current based elements are adders, multipliers, activation functions and their derivatives. The priorities for the design are both minimum power consumption and minimum silicon area. Simulated results for two networks are reported. I. Introduction. Several signal processing techniques used for the solution of massive and complex problems are based on the back-propagation algorithm ( 1, 3-51; for this reason, recently, many artificial neural networks have been reported (7-131. In order to take full advantage of the properties of these networks large systems must be built, hence for VLSI realisations very efficient building blocks must be used. The back-propagation algorithm is implemented by the architecture shown in Fig. 1 (l). The basic elements of the feedforward network are adders, activation (non- linear) functions and multipliers which are used to adjust the synaptic weights. In the feedback network, additionally to the building blocks used in the feedforward network, the derivative of the activation function is required.