Yield-Driven, Clock Skew Scheduling
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung‐Ping Chen, Kewal K. Saluja · 2005
Editor’s note: This article proposes clock skew scheduling as a tool to address causes of performance-related circuit yield loss. It is an interesting example of how managing circuit-level parameters can have a direct impact on yield metrics and, therefore, a clear example of the direction of DFM research.