Implementation Of Efficient 64-Point FFT/IFFT Block For OFDM Transreciever Of IEEE 802.11a
Murtuza Jeeranwala, Shruti K. Oza · 2014
This paper discuss an efficient approach for implementing 64- Point FFT/IFFT in the OFDM Transreciever .In our proposed design we will be incorporating a novel 32 bit word length 64 point FFT/IFFT processor developed primarily for the use in OFDM bases IEEE 802.11a wireless LAN based application. The 64 point FFT is realized by decomposing a 64 point FFT in two dimensional structure of 8 point FFT. This approach greatly reduces the number of complex multiplication required as compared to conventional radix-2 64 point FFT algorithm. Same unit can be used for both FFT and IFFT by just swapping its real and imaginary parts The main reason for our emphasis on FFT/IFFT processor in the design of IEEE 802.11a Transreciever is because of its ability to provide orthogonality to data carrier that forms the essence of any OFDM scheme.