Irreduiidaiit Sequential Macliiiies Via Optiiiial Logic S;\-iitliesis
S. Devadas, Hi-Iieuiig Tony, A. Richard Newton · 1990
It is well kiiowii that optimal logic syiitliesis can eiisure fully testa.ble combina,tional logic designs. In this paper, we show that optimal sequential logic syiitliesis cai produce irredundant, fully testable fiiiite sta.te nmchines. Test genera.tion algorithms cm be used to remove all the reduiida.1icies in sequential machines resnltiiig in a fully testable design. However, this iiiethod may require esorbit,aiit ainounts of CPU time. Tlie optimal synthesis procedure presented in this pa.per represents a more efficient approach to achieve 100 '% testability. Syiithesizing a. sequential circuit. froiii a State Transition Gmph description iiivolves the steps of sta.te niiniiiiiza,tioii, state assigiiiiieiit a.iid logic optiiniza.tion. Previous approaches to producing fully a.nd easily testable sequential circuits have involved the use of estra logic and constraints on state assigiiiueiit and logic optimiza.tioii. In this paper, we show tha.t 100% testability can be ensured without the addition of eztra logic and without constraints oii the state assignment aid logic optimization. Unlike previous synthesis a.pproaches to eiisuring fully testable niacliiiies, there is no areu/perfomzance penalty associated with this a.pproach. Tliis technique can be used in coiijuiictioii with previous approaches to ensure that the synthesized ma.chine is ea.sily testable. Giveii a Sta.te Transition Gra,pli specification, a logic-level autoiiia.toii tlnt is fully testable for all single stuck-at fa.ults in tlie coiubiiiatioiial logic uiithout access to the menzory elements is synthesized. This procedure represents an alterimtive to a Scan Design iuethodologv without the usual area aiid performance penalty associa.ted with the latter method.