FPGA Implementation of 32 point Radix-2 Pipelined FFT
Aruna Arya, Augusta Sophy · 2013
This paper presents an advanced method of implementing Fast Fourier Transform(FFT) using pipelining concepts. FFT is a technique which efficiently calculates the DFT by reducing the number of addition and multiplication operations taken place. In this paper ,in between the intermediate stages of every butterfly, pipelining is used to store the outputs of previous stages. Then, the development of 32-point FFT based on Decimation-In-Time radix-2 algorithm has been done. Pipelining is used to enhance the speed by decreasing the clock period and hence to improve the throughput of the FFT processor.