Architecting Hard Crossbarson FPGAs and Increasingtheir Area EfficiencywithShadow Clusters
Peter Jamieson · 2007
We explore thearchitecture ofon-chip hardcross- barsinFPGAsandshowthattheareaefficiency ofsuchFPGAs canbeimproved whencombined withshadowclusters (which are soft-logic LUT-based clusters thatarearchitected tositbehind themultiplier), asanexemplar ofanapplication circuit that appears less commonly inthedesigns targeting FPGAs. Themetric thatweseektoimprove isthefrequency that theneedforhardcrossbars mustappearintheFPGA'starget application suite fortheinclusion ofthehardcrossbar toappear tobearea-neutral. Forexample, we showthatthis break-even pointfora hard32full-way crossbar changes from32% of benchmarks needing torequire crossbars to9% forFPGAswith shadowclusters. I.INTRODUCTION Modernheterogeneous Field-Programmable GateArrays (FPGAs) employ hardspecific purpose circuits tonarrow the area, speed andpowergapbetween FPGAsandApplication- Specific Integrated Circuits (ASICs). Asdiscussed in(10), these structures havethepotential todramatically narrowthe areagap,if:first, thehardcircuit provides asignificant area, speed, orpowerbenefit whenimplemented ontheFPGA compared toimplementation using just theregular soft fabric, andsecond, thatthetarget application market hassufficient demandforthehardcircuit. FPGAnovice architects, whoexist inside FPGAcompanies (but typically outside themainarchitecture team) andoutside ofFPGAcompanies (andaretypically ASICdesigners orIP developers) will often propose theexactspecific hardcircuit thattheyareworking ontobeincorporated inthenext- generation FPGA,regardless ofthetwofactors above. These arguments canrageatlength, driven byinsufficient scientific andeconomic justification. Inthis paper, weuseacareful and scientific waytomeasuretheefficacy ofahardcircuit, and employ arecent architecture concept, called shadowclusters, toenhance theimpact ofahardcircuit that hasless demand initstarget market. Thenewarchitectural concept iscalled ashadowcluster,