Session 13 Overview
Mark Bauer, Dae-Seok Byeon · 2009
The most advanced lithography ever reported for a NAND flash memory uses MLC techniques to create a 32Gb device in a 34nm process. The highest density monolithic flash memory is also reported. Last year at ISSCC 2008, the conference saw for the first time a NAND flash design with 3 bits per cell. This year, a 64Gb NAND flash memory stores 16 levels in a cell for an unprecedented 4 bits per cell Two papers report on advancements in 3-bit-per-cell capability. One paper describes a 32Gb memory in a 48nm process and the other describes a 32Gb memory in a sub-35nm technology. In addition to advancements in density, two papers address power issues associated with building large memory subsystems. One paper removes charge pumps from the memory device and uses an off-chip inductor with an integrated voltage regulator to reduce die area and increase power efficiency. The other paper presents an inductive-coupling technique for wireless interfaces between a stack of discrete flash devices. The session starts with Paper 13.1 [Intel], demonstrating a 34nm 32Gb MLC NAND flash memory that uses a scaling-efficient array architecture with a mixed-string driver and a center-page buffer, resulting in 9MB/s program throughput. To minimize the routing impact, the datapath employs 4-way pipeline architecture and a pre-decoded redundancy-matching scheme. The analog architecture delivers precise and flexible voltages to optimize cell-disturbance mechanisms. Paper 13.2 [U Tokyo, Toshiba] describes how the power consumption of 3D integrated SSD is reduced by using a boost-converter-based adaptive-voltage generator. By optimizing the frequency and duty cycle of a digitally controlled oscillator, power consumption, voltage rise-time and the voltage-generation time decreases by 88%, 73% and 85%, respectively. The total power consumption of a NAND flash memory system is reduced by 68%. Paper 13.3 [Hynix] demonstrates 48nm 32Gb 8-level NAND flash memory that achieves a program throughput of 5.5 MB/s with a 4KB page depth. A pass-bit detector scheme is used in conjunction with a program algorithm to minimize program verify steps to improve write performance. With this innovation, program throughput improves by 30% as compared to the conventional case. The first 32Gb NAND flash memory designed for a microSD card is presented in Paper 13.4 [Toshiba, Sandisk]. The extended column scheme reduces the chip size by 1% because the approach eliminates the redundancy circuit such as column address latches and their control circuits. The row decoder circuit is designed to reduce the pump load, resulting in the reduced pump area. Paper 13.5 [Keio U, U Tokyo] presents an inductively coupled programmable bus using 0.18µm CMOS process for reduction of power consumption in SSD. The wireless interface using relayed transmission decreases the power consumption by 50%. This can be extended to interface many NAND Flash chips in parallel making the savings significant. In addition, I/O circuit layout area reduces to 1/40 th of the conventional wire bond approach and helps achieve a data rate of 2Gb/s.