Video Enhancement Algorithms on System on Chip
S. K. Srivatsa · 2012
This paper presents a way to improve the computational speed of video enhancement using low-cost FPGA-based hardware. To design real-time adaptive and reusable image enhancement architecture for video signals based on a statistical processing of the video sequence. The VHDL hardware description language has been used in order to make possible a top-down design methodology. Generic design methodology has been followed by means of two features of the VHDL: global packages and generic pass. Video processing systems like this one require specific simulation tools in order to reduce the development time. Real tine image processing in an application environment needs a set of low cost implementations of various algorithms. This paper presents a median filter based on a system on chip and working at video rate. It includes its own memory and can be used without any image memory for on line processing. The architectural choices have made it possible to design a small size chip with a high performance level. A VHDL test bench has been designed specifically for Video processing applications to facilitate the simulation process. A video enhancement processor concept is proposed that enables efficient hardware implementation of enhancement procedures and hardware software co-design to achieve high performance, low- cost solutions. The processor runs on an FPGA prototyping board.