Session 20 overview microprocessors
2002
The papers in this session show the conflicting demands placed on the microprocessor designer in the balance between performance, integration, and power efficiency. Circuit designers continue to reduce cycle times to permit higher and higher clock rates. Additionally, microarchitectural complexity continues to increase: This year, there are two papers in this session which introduce multithreading into mainstream microprocessor design. Designers of embedded CPUs face a slightly different set of challenges. The high degrees of integration can be used to implement complete system-on-chip (SoC) solutions where power consumption and time-to-market are important criteria. Reduced feature size permits large amounts of memory to be integrated along with a microprocessor, and three papers demonstrate this. In Paper 20.6, a total of 3.3MB of cache are included across 3 levels of memory hierarchy. Paper 20.6 also shows how processor designers need not necessarily resort to deep pipelines to increase clockrate operation. Over 1GHz has been achieved with only 8 stages in the pipe. In Paper 20.3, a migration to 0.13µm technology permits a 1MB level-2 cache to be integrated, along with many other new features.