Transactions Briefs An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis
Vojin G. Oklobdzija · 1994
Abstmet-A novel way of implementing the Leading Zero Detector (LZD) circuit is pmsented. The implementation is bad on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. We designed a 32 and 64 bit leading zero detector circuit in CMOS and ECL technology. The CMOS version was designed using both logic synthesis and an algorithmic approach. The algorithmic implementation is compnred with the results obtained using modern logic synthesis tools in the same 0.6 pm CMOS technology. The implementation based on an dgorithmic approach showed an advantage compared to the results produced by the logic synthesis. ECL implementation of the 64 bit LZD circuit was simulated to perform in under 200 pS for nominal speed. I. INTRODUCTION In any floating-point processor normalization is a required operation. It consists of an appropriate left shift until the first nonzero digit is in the left-most position. The amount of shift is determined by counting the number of zero digits from the left-most position until the first nonzero digit is reached. The exponents are appropriately decremented for the shift amount. The normalization is usually performed before storing the numbers in the register file (memory), commonly referred to as post-normalization, and referred to as prenormalization before the operation is performed. In both cases, the special circuit implemented (in hardware) to detect the number of leading zeros is referred to as a Leading Zero Detector (LZD).