Fail-Safe MultiBoot Reference Design
Jim Wesselkamper · 2009
This application note describes a reference design that adds fail-safe mechanisms to the MultiBoot capabilities of the Extended Spartan®-3A family of FPGAs (Spartan-3A, Spartan-3AN, and Spartan-3A DSP FPGAs). The reference design configures specific FPGA logic via an initial bitstream that determines which application (by alternate bitstreams) to load. The decision as to which bitstream to load, if an alternate is loaded at all, is based on the bitstream revision, the number of prior configuration attempts, and the integrity of the alternate bitstreams. The algorithms that test bitstream integrity and select the bitstream image to load are implemented using a PicoBlaze™ controller. Additional independent modules manage communication with the Internal Configuration Access Port (ICAP) and the Serial Peripheral Interface (SPI) flash device.