FPGA IMPLEMENTATION OF 4D-PARITY BASED DATA CODING TECHNIQUE
Vijay Tawar . · International Journal of Research in Engineering and Technology · 2015
The scenario of communication systems is changing with the immense development of electronic devices and the increasing demand of data in communication systems.When the communicating data follows the wireless path in its communication channel then the presence of the electromagnetic signals in the communication media can effects the integral value of the signal and may lead to the wrong reception of the data at the receiver side.This wrong reception is further reflected as the wrong processing data to generate the undesired system output.So, the communication systems are required to have some hardware or software resources to detect the effects of the environmental electromagnetic signals, called noise.A number of techniques have been proposed to estimate the effect of noise as well as the actual value of the transmitted data.One of the simplest methods used to identify a change in the transmitted digital data stream is by adding even or odd parity bit with the transmitted data and checking verifying its authenticity at the receiver end after receiving the data.A single bit parity scheme only informs about an odd bit change in the transmitted data.One of the implementation methods of using the similar concept for noise effect identification and correction is by using 4-dimensional parity method.This method involves generation of parity bits of a pre-accumulated data in four directions.Each of the data bit is used to generate 4-parity bits.The involved method can be effectively used to identify and correct 3-bit of error in the transmitted data with the help of the parity bits.In the proposed work the same error detection and correction method is simulated on a field programmable gate array device using Xilinx ISim Tool.