Testability analysis of asynchronous circuits designed from signal transition graphs
Chusak Khomentrakarn · 1995
This work investigates testability of asynchronous circuits and its relation with signal transition graphs (STGs), using a state based approach on non-scan asynchronous circuits. In addition to the testability characteristics studied, this work suggests some test generation techniques for asynchronous circuits designed from STGS. An event fault, interpreted as either a stimulating fault or an inhibiting fault of a transition, is used to cover the stuck-at-fault (SAF) behavior of an asynchronous circuit. An advantage of such analysis is that test vectors for an inhibiting fault can be obtained from operations on a signal transition graph (STG) or a state graph (SG) rather than simulation at the circuit level. A test vector for a test state is represented in an STG by a test marking for each event fault. The lock relation of signals is a property proposed for hazard-free asynchronous circuit's synthesis. However, it is found that there is a special case of the lock relation that can prohibit the testing of some faults, the introduction of which cannot be avoided by the circuit level mapping. Some independent undetectable faults due to uncontrollable test states however can be detected if the reset state is the test state. Using a minimized two-level sum-of-products representation, each literal in a cube of the sum-of-products form is found to have its own function corresponding to the STG. Consequently, four types of literals are defined and their relations with the SAF behavior over the stimulating/inhibiting fault are analyzed. Although factorization of a logic equation binded to a C-element or a set-reset (SR) flip-flop is not always possible, a correct implementation on a set-dominant SR flip-flop is guaranteed. (Abstract shortened by UMI.)