Design of High Speed, Area Efficient, Low Power Vedic Multiplier using Reversible Logic Gate
A. Shifana Parween, S. Murugeswari · 2014
Abstract — A systems performance is generally determined by the speed of the multiplier since multiplier is one of the key hardware component in high performance systems such as FIR filters, digital signal processors and microprocessors etc. Multipliers have large area, long latency and consume considerable power. Hence good multiplier architecture increases the efficiency and performance of a system. Vedic multiplier is one such high speed, low area multiplier architecture. Further implementing this in reversible logic reduces power. In this paper a 4 X 4 Vedic multiplier is designed using reversible logic gates which is efficient in terms of constant inputs, garbage outputs, quantum cost, area, speed and power. The design is simulated using Verilog.