FPGA Implementationof Secret Communication with VHDL
D. Anvesh Kumar, Y. V. AdiSatyanarayana, P. Prasannamuralikrishna, M. Tecch · 2012
This paperpresents a communication of data secretly using AES Algorithm i.e we first send the data (plain text) and the key which is of 64 bit into the encryption process .The output of this process will be cipher text. This cipher text is then fed into the decryption process and then the data (plain text) is got as output. In this project we add the key and shuffle the data it is very hard for the unknown person to find out the original data. Since for each key there will be a change in the cipher text and so the person has to know the key in order to find out the original data.The AES algorithm involves the process of giving the data and key as input to the encryption block and then implementing several blocks such as key schedule block, control block, round function block, etc.In this project, we aim at designing a high speed and high performance but cost-effective FPGA based processor which encrypts and /or decrypts the data that has to be transferred from one PC to the other, based on the Advanced Encryption Standard (AES) algorithm.