Transactional Value Prediction
Fuad Tabba, Andrew W. Hay, James R. Goodman · 2009
This workshop paper explores some ideas for value prediction and data speculation in hardware transactional memory. We present these ideas in the context of false sharing, at the cache line level, within hardware transactions. We distinguish between coherence conflicts, which may result from false sharing, from true data conflicts, which we call transactional conflicts. We build on some of the ideas of Huh et al. [1] to speculate in the presence of coherence conflicts, assuming no true data conflicts. We then validate data before committing. This dual speculation avoids aborting and restarting many transactions that conflict through false sharing. We show how these ideas, which we call Transactional Value Prediction, can be applied to a conventional best-effort hardware transactional memory. Our preliminary model, β-TVP, does not alter the underlying cache coherence protocol beyond what is already present in hardware transactional memory. β-TVP requires only minor, processor-local modifications to a conventional best-effort hardware transactional memory. Simple benchmarks show that β-TVP can dramatically increase throughput in the presence of false sharing, while incurring little overhead in its absence. 1.