Reference System: Optimizing Performance in PowerPC 440 Processor Systems
James Lucero · 2008
This reference system demonstrates improving system performance in the PowerPC ® 440 Processor Block on the Virtex ® -5 FXT FPGA. In this reference system optimizing performance for embedded DMA solutions is discussed. The XPS Central DMA master interface can be connected to the Processor Local Bus (PLB) v4.6 on either PLB Slave 0 (SPLB0) or PLB Slave 1 (SPLB1). Parameters for the XPS Central DMA are modified for the DMA engine to allow for parallel reads and writes through the crossbar. For HDMA, setting threshold values for interrupts and changing addresses in main memory for Buffer Descriptors (BD) and transmit/receive buffers is discussed. A simple loopback core is connected to the LocalLink interface on one HDMA. In addition, performance cores for PLB v.4.6 master interfaces and HDMA are included in the system to measure system performance before and after system optimizations. Two stand-alone software applications are included to demonstrate DMA transactions for XPS Central DMA and HDMA to DDR2. In addition, during these DMA transactions, the performance is measured between certain conditions. For XPS Central DMA, the performance is measured between PLB_PaValid and when the XPS Central DMA provides an interrupt (DMA transactions are complete). For HDMA, the Tx and Rx channels are measured between the first frame’s start of frame (SOF) and the last frame’s end of frame (EOF). This application note describes how to obtain latency numbers across the crossbar, obtain performance numbers before optimizing the system/software applications, optimizing the system/software application for performance and obtaining performance numbers with the optimized system. The Xilinx ML507 Rev A board is used for this reference system.