HIGH SPEED VLSI ARCHITECTURE FOR NON SEPARABLE BLOCK BASED LIFTING WAVELET TRANSFORM
Usha Bhanu N, Arul Gnanaprakasaam Chilambuchelvan · 2014
The inherent advantage of the in-place computation of the lifting based DWT over the conventional convolution method makes it suitable for efficient hardware implementation with lower computational complexity. The proposed paper uses Non Separable block based method to derive the VLSI architecture for the two dimensional DWT. In separable lifting DWT, the desired filter coefficients at each level are dependent on previous output level and this introduces delay or latency in DWT decomposition. The proposed Non–separable architecture contains floating point multipliers and adders based on IEEE 754 single precision format. It requires six lifting steps for the implementation of 9/7 lossy lifting DWT and the latency is reduced when compared to separable DWT. It is suitable for handling a parallel block of 4×4 input image coefficients at each level, for achieving higher speed and dynamic accuracy. The architecture is coded in Hardware Description Language and implemented in Altera Cyclone II FPGA. The critical path delay for the proposed Non Separable architecture is 3.189 ns, with a speed of 313.58 MHz. The total thermal power dissipation of the architecture is 128.59 mW, suitable for low power embedded multimedia applications.