A New Class of Adder for RNS
Rachit Patel, Mohammed Benaissa, Said Boussakta · 2007
þ 1Þ addition. The algebraic properties of such moduli are exploited in the derivation of the proposed fast adder architecture. Actual VLSI implementations using 130nm CMOS technology show that our adder significantly outperforms the most competitive generic modular adder design over the entirety of the power-delay-area space. Index Terms—Computer arithmetic, modular adder, parallel-prefix adder, residue number system, VLSI.