High-Speed Programmable Logic Arrays in Technology
E. Hebenstreit, Karlheinrich Horninger, Esfi Sos · 1976
Exploratory programmable logic arrays (PLA's) operating up to a clock frequency of 22 MHr have been realized and successfully operated. These PLA's use dynamic logic gates and are built in epitaxial- silicon films on insulators (ESFI) silicon-n-sapphire (SOS) technology. The problems arising with the use of these dynamic gates in a two-stage logic array are discussed and different circuits are presented. The ad- vantage of these circuits, in addition to their high speeds, is redueed power consumption, and the possibility to determine the number of feedback loops when the array is personalized, The features of the cir- cuits are compared with each other and with a complete PLA deseribed in an earlier paper (6). The results gained from computer simulations agree reasonably well with the experimental results. HEN designing a programmable logic array (PLA) to implement random logic, speed considerations play a very important role. Since a PLA has a predetermined regular structure, which is personalized with the help of a single mask to produce the required combinatorial and sequen- tial logic functions, the number of product terms actually used will generally be less than the total product terms of the PLA. This results in the fact that a PLA is-in most applications-a circuit with redundancy. The load capacitances which the ac- tive devices of a PLA have to drive are, therefore, on the aver- age higher than in a custom designed logic circuit. Because of this, a fast PLA should be built in a technology having very small stray capacitances. The epitaxial silicon films on insula- tors (ESFI) silicon-on-sapphire (SOS) technology can be used very advantageously and large PLA's built with it have reached speeds comparable to the operating speeds of bipolar PLA's (2) . Another consideration in designing PLA's is power consump- tion. As the arrays get larger and larger, the power dissipation cannot be neglected. From this consideration, PLA's using in- sulated gate Held-effect transistors (FET's) are better suited for large arrays than bipolar PLAYS. At the same time a circuit with low power dissipation should be used. In this paper a dynamic principle for PLA's using metal-oxide semiconductor (MOS) FET's will be described. Using this principle, different PLA circuits which can operate at very high speeds and dissipate only very little power can be built.