Cypress Delta39K TM - A Memory-Rich, High Performance, Scalable CPLD
Andrew Kenningsl, Haneef Mohammed, Joseph P. Skudlarekl, Bing Tian · 2000
The architecture of the Cypress Delta39K CPLD family is described', including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including Macrocells, 1/0 Cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fit into a representative device using the Warp TM6. U software'.