UltraController-II: Minimal Footprint Embedded Processing Engine
Punit Kalra · 2005
Summary UltraController-II is a minimal footprint embedded processing engine based on the PowerPC™ 405 (PPC405) processor core embedded within Virtex™-4 FX and Virtex-II Pro Platform FPGAs. Computing performance is maximized and FPGA resource usage minimized by running code strictly from the integrated PPC405 caches. General-purpose input/output (GPIO) is available directly from the PPC405 core. Interrupt handling is provided for a user defined external interrupt line, a programmable interval timer (PIT), and a fixed interval timer (FIT). System designers can easily incorporate the UltraController-II black-box processing engine into larger ISE designs to gain additional degrees of freedom by balancing usage of the high-performance FPGA fabric with the algorithmic flexibility of software. This application note presents the features and benefits of the UltraController-II along with a brief overview of the tutorial applications included with the design. The accompanying tutorials and reference designs include VHDL, Verilog, and example C-code applications with step-bystep procedures. Performance characteristics and how to field an UltraController-II system using Xilinx configuration solutions are also provided.