AREA OPTIMIZED SOLUTION FOR STRUCTURED ASIC DYNAMIC RECONFIGURABLE PLA
Traian Tiberiu Tulbure · 2010
This paper proposes a new area optimized architecture for dynamic reconfigurable logic array with implementation on structured ASIC. Reconfigurable architectures allow the dynamic reuse of the logic blocks by having more than one on-chip SRAM bit controlling them. Thus, rather than the time needed to reprogram the function of the device from external memory which is the order of milliseconds logic block functions can be changed by reading a different SRAM bit which only takes time of order of nanoseconds. Programmable Logic Array (PLA) structures can be implemented on Structured ASIC technology to eliminate the constraint given by fixed wire routing. Adding dynamic reprogramming to the structure implies adding a big distributed memory that affects both array utilization and device performance. We are proposing in this paper a solution that uses the available block RAM memory to reduce area utilization and improve performance for dynamic reconfigurable PLA. The implemented PLA array presents dynamic reconfiguration with 16 configurations contexts for classical PAL 22v10 structure. The contexts are stored in inactive block RAM memory allowing fast context change. The implementation results validate the proposed structure showing high-speed frequency operation and area reduction of about 30% compared with same PLA structure implemented with distributed memory.