Enabling High-Speed Radio Designs with Xilinx All Programmable FPGAs and SoCs
Michel Pecot · 2014
This white paper describes the capabilities of Xilinx® 7 series All Programmable FPGAs and SoCs to implement high-clock-rate signal processing functionality typically used by the datapath of digital radio applications. A clock rate higher than 500 MHz can be supported on a mid-speed grade 7 series device with almost 100% of the logic slices, more than 90% of the DSP48 slices, and 70% of the block RAMs utilized. This requires the designer to follow some rather simple design rules that cover both algorithmic and implementation aspects. These rules are reviewed in the paper. Although almost 100% of the slices can be used at 500 MHz for pure datapath designs, only 75% to 80% of the logic resources (LUTs) are effectively occupied, which essentially relates to routing and control set resource constraints. A higher LUT utilization ratio is achievable with the next-generation 20 nm UltraScale™ architecture, which provides significantly increased capabilities.