INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & MANAGEMENT TWO DIMENSIONAL LOW LATENCY NOC ROUTER BY WORMHOLE SWITCHING
Rajesh Nema, Teena Raikwar, Prerna Suryavanshi · 2012
Network on Chip (NoC) is an approach to designing communication subsystem between intelligent property (IP) cores in a system on chip (SoC). Packet switch ed networks are being proposed as a global communication architecture for future system-on-chip (SoC) design s. In this project, we propose a design and impleme nt a wormhole router supporting multicast for Network-on-chip. Wormhole routing is a network flow control mechanism which decomposes a packet into smaller flits and delivers the flits in a pipelined fashion. It has good performance and small buffering requirements. The i mplementations are at the RT level using VHDL and they are synthesizable. First, based on virtual cut thro ugh router model, a unicast router is implemented a nd validated and based on the wormhole switching mode the multicast router architecture is designed and implemented . A Wormhole input queued 2-D mesh router is created to verify the capability of our router.