ON THE FIXED-POINT ERROR ANALYSIS AND VLSI ARCHITECTURE FOR FS1016 CELP DEClODER
Careri China · 1997
In this paper, the fixed-point accuracy analysis and VLSI architecture of FS1016 CELP decoder are presented. The code excited linear predictive (CELP) coder is the most effective technique among various linear predictive coding methods for speech compression. Hence to design a low cost and low power CELP decoder chip for the portable systems and wireless digital communication environment becomes increasingly important. The decoder VLSI architecture can achieve (1) excellent accuracy results due to the accuracy studies for the finite word length, (2) power saving and high speed operations resulting from the combined advantages of pipeline, current processing for LSPs interpolating and cosine operation, (3) t,able size reducing by applying the memoryless realization for stochastic codebook and partial sums techniquc, and (4) specification satisfying the FS1016 CELP coder.