A Configurable System-on-Chip Device Facilitates Customization and Reuse
Danesh Tavana, Steven K. Knapp · 2000
Time to market pressures, increasing system complexity, and smaller process geometries, are creating a market vacuum that will be increasingly addressed by an important emerging category of devices: the Configurable System-on-Chip (CsoC). These application specific programmable devices (ASPP) are single chip combinations of microprocessors, memory, dedicated peripheral functions, and embedded programmable logic. They provide unprecedented time-to-market benefits and field customization for the electronic systems of this upcoming decade. Integration of microprocessors, memory, peripherals, and programmable logic is made possible with a new bus architecture called the Configurable System Interconnect Bus (CSI) developed at Triscend Corporation. The Configurable System Interconnect Bus was specifically designed to facilitate re-use, guarantee timing, increase system throughput, and reduce system debug time in applications that require intense time-to-market and field upgrade. AUTHORS/SPEAKERS Danesh Tavana VP Engineering, Triscend Corporation Danesh Tavana has 19 years of experience in system-level and semiconductor design. Prior to co-founding Triscend on May 1997, he spent 5 years at Xilinx on various FPGA design and soft-core development projects. Before Xilinx he worked for NeXT computer, Inc. and Adaptec on various CMOS ASIC projects. Danesh began his career at Monolithic Memories in 1981 as a Bipolar IC Design Engineer. He holds eight US Patents and received his BSEE from U.C. Berkeley, and MSEE from Santa Clara University. Steven Knapp Vice President of Applications, Triscend Corporation Steve has been actively involved in programmable logic applications for more than 14 years. Prior to joining Triscend in 1997, Steven had founded OptiMagic, a company specializing in developing software and intellectual property for programmable logic. Before that, he spent 11 years at Xilinx, where he held various management and sales positions. Steven holds several patents in parameterized logic design entry and has a BSc in materials science from MIT. Introduction Six competing requirements challenge the embedded systems designer: time-to-market, performance, cost, physical size, power consumption, and product features (Figure 1). The designer's task is to find the best possible compromise between these requirements in order to deliver the most effective product to the customer. Figure 1. Embedded Systems Challenge For many applications, Triscend's Configurable System on Chip (CSoC) products offer designers a more attractive balance between these factors than alternative solutions. Design re-use, and field upgrade through remote software download, when combined with a CSoC device, fundamentally change the rules of embedded system design by breaking the link between time to market and product features. CSoC Introduction Embedded system designers develop products with a specific function or application in mind. In almost every application there is a central processing unit that is responsible for the overall system’s supervision, handling of complex state machines, and number crunching algorithms. The central processor also manages the system’s memory and I/O, which are the peripherals that interface to various entry or display devices. In contrast to personal computers, the embedded system applications are usually differentiated in both hardware and software. Unlike the PC chip sets and prevailing standards around it, the embedded system world is plagued with innumerous design choices and lack of standards. Triscend’s CSoC device is an ideal single chip device for the embedded system designer who wants both hardware and software flexibility on a single extensible platform. Imagine if as a system designer you could begin your design with a popular industry-standard processor that is supported by leading 3 party compiler, assembler, and debugger tool vendors. The processor is a familiar, proven architecture with a large availability of freeware applications. The processor’s performance is boosted through pipelining in a “Turbo” mode operation, and by employing advanced CMOS processing technologies. What if you also had an integrated DMA controller that offloads the processor from large data transfers, freeing it for more important tasks? A glue-less interface to external byte-wide Flash, EPROM, or SRAM improves performance and eliminates external latches that are typically required in time-multiplexed address/data bus interfaces. In applications requiring even higher performance with lower power dissipation, an on-chip SRAM ranging in density from 8K bytes to 64K bytes provides data or code storage for the processor, and data buffer space for the DMA controller. What if the system came with an integrated onchip bus specially designed to insure single cycle data transfers and programmable address decoding for the peripherals embedded in the chip? This bus is specially designed to facilitate “soft module” re-use by abstracting the processor specific signaling requirements from the peripherals, and by supporting a friendly drag and drop software tool for developing micro-controller derivatives. Programmable I/O (PIO) pins operate independently from the bus and are tightly coupled to an on-chip embedded programmable logic core. Flexible pin assignment for optimum PCB layout and a host of field programmable options like output drive strength, slew rate control, pull up, pull down, registered I/O, or low power operation are some of the user selectable features for each package pin. Finally, what if all this was offered with a large amount of on-chip programmable logic with sophisticated built-in system debugging hardware that includes a JTAG interface and a breakpoint unit? And what if the device came with a rich debugging environment where the device can be altered in the field infinitely and debugged using standard logic debugging or processor ICE debugging techniques? Now you can have a device that does exactly that. Triscend Corporation’s E5 device (Figure 2) is a single chip CSoC that is the ideal embedded system platform for creating flexible, fast timeto-market applications. Implementing the E5 as a dedicated logic chip with only a small area of re-configurability provides one to two orders of magnitude more efficiency in silicon area than a similar implementation in a pure programmable logic device. Other obvious advantages offered by the integration include increased performance and lower power. An important architectural feature of the E5 CSoC is the Configurable System Interconnect (CSI) bus that allows each resource on the bus to communicate to other resources, thus leveraging and building upon the existing resources. Figure 2. Triscend’s E5 Configurable System on Chip Block Diagram CSI Bus Introduction The configurable system interconnect (CSI) bus is designed to facilitate design re-use within the configurable system logic (CSL). The bus is distributed throughout the CSL in fixed logic. It is connected and operates with all system masters including the processor, DMA controller, JTAG interface, and the external Memory Interface Unit (MIU). Memory mapped and DMA slaves may be implemented to handle data transactions. User logic may obtain the services of the processor and DMA controller as proxy masters through an interrupt or DMA request respectively. The user is assured that the bus will reach any logic implemented within the CSL. The maximum bus performance specification can be met regardless of the placement algorithm’s quality of results. The primary objective in the design of this bus was to make it easy to use. The bus operates synchronously. The default transaction duration is one clock cycle. Wait states may be added when necessary. The appropriate bus signals may be configured to connect to the CSL logic as required for the user’s design. Additionally, the synchronous decode of addresses and commands is handled for the user by selectors. There are many selectors distributed throughout the CSL. Each selector provides simple read and write signals to be routed to the user logic. The addresses and commands that a selector responds to may be individually configured. CSI Bus Architecture The bus operates synchronously and supports multiple masters and slaves, DMA, and wait states. The bus is pipelined, has separate write and read data paths, uses multiplexed or logical OR networks to combine signal sources, and supports a fast default cycle with optional wait states when necessary. A round-robin arbitration scheme is implemented for masters. The slave side includes multiple decoded and qualified read and write enable signals generated by selectors. A logical bus architectural diagram and signal flow is shown in Figure 3. There are four primary bus segments: master read/write, and slave read/write related to the distribution and collection of the bus signals prior to the pipeline registers. The multi-source instances of all signals in each collection segment are combined via logical OR gates or multiplexed networks into a consolidated bus. This prevents power consumption concerns in the event of any contention that is typical of tri-state bus structures.