A RECONFIGURABLE FAULT-TOLERANT SYSTOLIC SIGNAL PROCESSOR
R.R. Shively, Allen L. Gorin · 1989
We describe a pdel computer architecture targeted at signal pattern analysis applications. scalable to configurations capable of TeraFLOP (1012 floating point operations per second) throughput. An impoltant anribute of the architecture is its low intercowction ovehead, making it well-suited to miniaturization via advanced packaging. Preliminary design and thermal tests project a computing density of 300 GigaFLOPS per cubic foot. llx architecture is reconfigurable as a tree machine. cm or more rings, or a set of linear systolic arrays. Fault-tolennce is achieved by embedding these topologies within a four-connected lattice, growing around any faults. A performance model is derived analyzing the impact of skewness of the embedded uees on execution time of parallel panem recognition algorithms. 1.