Efficient Routing Implementation of Programmable Network on Chip on FPGA using Circuit Switching Approach
Parag Parandkar, Purnima Khandelwal, Geetesh Kwatra, Sumant Katiyal, M. Tech · 2015
More and more complex and larger system on chips are getting developed as a result of increase in chip density following Moore's law. Advanced SoCs have in their shelf significantly noticeable communication mechanisms. NoC has solved the scalability problems to a larger extent compared to bus based interconnect. NoC has been providing a back bone infrastructure for System-on-chips since long. Among the available communication matrices NoC has helped tremendously in the communication performance enhancement. NoC research majorly involves work on packet switching, though at the same time circuit switching assures high communication rates and predictable communication latencies. The current research is targeted towards implementation of NoC architecture for FPGA based designs using circuit switching approach. Proposed implementation is termed as enhancement of light weight circuit switched architecture. The programmable NoC architecture is being implemented using VHDL and synthesized on the Virtex-5 XC5VLX20T package FF323 device at 139 MHz. It provides sufficient customization on the number of ports, nodes and amount of data. Performance improvement over the existing implementations has been validated by the experimental synthesized results.