FPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router Architecture
Nam-Khanh Dang, Thanh-Vu Le-Van, Xuan‐Tu Tran · 2011
The Network-on-Chip (NoC) paradigm has recently been known as a promising solution for designing large complex Systems-on-Chip (SoCs), especially when the semiconductor technology turns into 3D integration era. This paper presents the design of a NoC router architecture which provides low latency, high throughput communication. The NoC router architecture is implemented on a Xilinx technology FPGA chip for prototyping purpose with an obtained latency of 8.1 ns and a maximum throughput of 123Mflits/s on each communication channel. These results can be improved when the design is implemented with ASIC design flows. Keyword: Network-on-Chip (NoC), On-chip communication, router architecture.