Tree-Based 3-D Topology for Network-On-Chip
Mohammad Yahiya Khan, Sapna Tyagi, Mohammad Ayoub Khan · 2014
3 Abstract: The increasing demand of numerous applications in consumer electronics has increased the number of computing resources in single chip. In such scenario, application needs many computing resources to build a System-on-Chip (SoC).Therefore, interconnection among Intellectual Property (IP) cores becomes another challenging issue. The performance of the network is measured in terms of throughput. The throughput and efficiency of interconnect depends on network parameters of the topology.Therefore, topology of any communication networks has an important role to play for efficient design of network. This works considers the design of an efficient tree-based topology to apply for Network-on-Chip. The degree of proposed topology is 25% less than the torus along with drastic reduction in the diameter of proposed topology. We have obtained reduced degree for proposed topology that varies from 3 to 6 for the network with k layers, while the diameter of topology is obtained as D= (2n-1) + k - 1. We have also presented and simulated an efficient routing algorithm that computes shortest path in the network.