MINIMIZATION OF TRANSITION DENSITY IN VLSI TESTING BY MULTIPLE ARRAYS OF SIC VECTORS WITH REDUCED ARCHITECTURE
T. Raju, Oggi Sudhakar, M. Tech · 2014
During its Lifetime, a digital system is tested and diagnosed on numerous occasions. For the system to achieve its proposed mission with high availability, testing and diagnosis must be speedy and effective. The Efficiency of a Circuit Depends upon reliability of generating output sequences and Presence of Delay between applied inputs to the Output Response. The circuit testing is performed with Test pattern generation methods. The TPG methods are implemented by the LFSR (Linear feedback shift Register) based methods for the Built in Self Test (BIST) which will reduce the complexity of VLSI Testing. A major consideration factor of these architectures is that the pseudo random patterns generated by the LFSR lead to significantly high switching activities in the CUT, which can more results in power dissipation. The excessive power dissipation is effectively reduced by MSIC patterns. MSIC pattern generators depend upon the applied vector length SIC vectors are generated with respect to the applied test vector length. MSIC pattern generator is implemented by the Johnson ring counter.