VLSI IMPLEMENTATION OF PHYSICAL LAYER CODING USED IN SUPER SPEED USB USING VERILOG
A. S. Srinivasarao, D. Srinivasa Rao · 2012
3 Assistant. professor, Dept of ECE, AITAM, Tekkali, A.P Abstract- This project implements the DC balanced 8B/10B coding used in Super speed USB with employ a very fast FPGA from Xilinx family is proposed. This technique can be used by other high speed serial buses such as PCI Express, IEEE 1394b, Serial ATA, SAS, Fiber Channel, SSA, Gigabit Ethernet, In fini Band, XAUI, Serial Rapid IO, DVI and HDMI (Transition Minimized Differential Signalling)that use the same coding. Using the look-up table and memory with fast technique made this design efficient to be implemented. Moreover, the proposed method has very low complexity and fast to execute with minimum logic and also easy to implement. The Scrambling and descrambling modules are added in the above modules to support USB 30 physical layer transactions. The code is implemented in VERILOG