A programming system for parallel digital signal processor networks
Todd A. Cook · NCSU Libraries Repository (North Carolina State University Libraries) · 1989
A Programming System for Parallel Digital Signal ProcessorNetworks (Under the direction of Thomas K. Miller III.)A system, called PaLS, has been developed for programming parallel digital signal processor networks.This system consists of a psuedo-compiler for a newly designed, C-like language (called DFC), an algorithm partitioner, a scheduler, and a code generator.An algorithm designer writes a program in the DFC language that implements his/her algorithm; the programming paradigm is conventional and sequential.The DFC compiler then converts the program to an intermediate format that represents the program as a flow-graph.The flow-graph is then partitioned using mean field annealing, and the nodes assigned to each partition are scheduled to achieve maximum processor utilization.Finally, a C program for each processor is generated using the partitioning and scheduling results.