Memory Efficient Architecture For High Speed Fir Filter Using Distributed Arithmetic
M. Satya Sai Ram, M. Devendra Reddy · 2013
This paper presents the realization of memory efficient architecture using Distributed Arithmetic (DA) for implementation of Finite Im- pulse Response (FIR) filter. Here, the multipliers in FIR filter are replaced with multiplier less DA based technique. First, the theory of DA is de- scribed. In this technique, pre-computed values of inner product are stored in LUT, which are further added and shifted with number of iterations equal to the precision of input samples. But the exponential growth of LUT with the order of FIR filter, in its basic structure, makes it prohibitive for many applications. An improvement over the basic DA structure is presented in this paper, by the use of partitioning of LUT to the desired length. Architecture of 32 tap FIR filter is presented, with different length of partition of LUT. Design implementation and synthesis result shown the im- provement in speed of operation as well as saving in memory, with more number of partitions. The proposed architecture provides an efficient memory-time-power implementation which involves significantly less latency and less area-delay complexity when compared with existing struc- tures for FIR Filter. Keywords— Distributed Arithmetic (DA), Field programmable gate arrays (FPGA), Finite Impulse response (FIR), Look Up Table (LUT), Partition. —————————— ——————————