Performance Comparison of Non-Redundant and Redundant FPGA based Unfolded CORDIC Architectures
Burhan Khurshid, Gulam Mohd Rather, Hakim Najeeb-ud-din · 2012
Digital Signal Processing algorithms are known to provide an unbeatable performance in processing the real world data. To assure this real-time throughput requirement, DSP algorithms need to be implemented and optimized for sustaining high data rates while maintaining a flexible tradeoff with performance parameters like area, speed and power. CORDIC is one such hardware efficient shift-add algorithm that is used for computing a wide variety of trigonometric, hyperbolic, linear and logarithmic functions. This paper implements the conventional non-redundant CORDIC architecture in parallel and pipelined styles. The comparison is then made against the modified CORDIC architecture, which is based on redundant arithmetic. It is concluded that redundant structures offer better performance than non-redundant architectures in terms of amount of hardware circuitry and resources required (on chip area); the speed of execution (throughput or operating frequency), and the amount of power dissipated on chip. All three designs are designed in VHDL, simulated using ISIM simulator and implemented using Xilinx 12.4 FPGA synthesis Tool.