Bus Functional Model (BFM) Simulation of Processor Intellectual Property
Lester Sanders · 2006
This note provides the flow for simulating Processor Intellectual Property (PIP) cores using Bus Functional Models (BFMs). The PIP cores used as examples include a new core, existing cores, and a sample system core. The simulation results of the OPB GPIO core are given to illustrate the capability of a BFM simulation. An introduction to writing stimuli for BFM simulation using a Bus Functional Language (BFL) in conjunction with a VHDL test bench is given. The example designs are intended to aid in the understanding the functionality of PIP cores. The comments in the code indicate the function being verified. The user can learn techniques for writing test benches/BFLs by reading and re-using the example code. The references provide information for users interested in writing complex or exhaustive test bench/BFLs. Included Files This application note includes BFM simulation files: www.xilinx.com/bvdocs/appnotes/xapp516.zip