e Gain from Data and C mination in Embedded
Valeriu Codreanu, R. Hobincu · 2010
This paper presents a way of performance in embedded processors b multithreading interleaved execution model th to any Instruction Set Architecture. U techniques as superpipeline or branch predic for embedded machines due to their inheren will show that by removing dependencies with thus eliminating the need for extra hardw keeping the overall coherence, there will be a in performance (up to 450%) and also a de power consumption. Also, this approach w backwards compatibility with the software l keep the software changes to a minimum.