for Energy Efficiency* Optimization of High-Performance Superscalar Architectures
Victor V. Zyuban, Peter Michael Kogge · 2000
In recent years reducing power has become a critical design goal for high-performance microprocessors. This work attempts to bring the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for poweroptimization at the micro-architectural level. First, major targets for power reduction are identified within superscalar microarchitecture, then an optimization of a superscalar micro-architecture is performed that generates a set of energy-efficient configurations forming a convex hull in the power-performance space. The energy-efficient families are then compared to find configurations that dissipate the lowest power given a performance target, or, conversely, deliver the highest performance given a power budget. Application of the developed methodology to a superscalar microarchitecture shows that at the architectural level there is a potential for reducing power up to , given a performance requirement, and for up to performance improvement, given a power budget.