High-Level Test Generation for Gate-Level Fault Coverage
Nitin Yogi, Vishwani D. Agrawal · 2006
In this paper we introduce a spectral method of register transfer level (RTL) test generation for sequential circuits. We define RTL faults as stuck-at faults on all primary inputs, primary outputs, and flip-flop terminals. Test vectors generated to cover the RTL faults are analyzed using Hadamard matrices. The analysis determines the amplitudes of prominent Walsh functions and the random noise level for each primary input. That information is then used to generate vectors for any gate-level implementation. At the gate-level, a fault simulator and an integer linear program (ILP) are used to compact the test sequence. We give results for three ITC’99 and four ISCAS’89 benchmark circuits. Each ITC’99 circuit was synthesized two ways, separately for area and delay optimization. The RTL spectral vectors performed equally well on both implementations. When compared to a gatelevel ATPG, the coverages of RTL vectors were similar and in many cases RTL vectors produced equal or higher coverage in shorter CPU time. 1.