Partitioned Register File Designs for Clustered Architectures
Yukinori Sato, Kenichi Suzuki, Tadao Nakamura, Aramaki Aza Aoba · 2006
The clustered architecture, where the conventional monolithic register file is partitioned into several smaller register files, is one of the candidates for the future high performance processor architectures. The aggressive partitioning can reduce the access time of the register file. On the other hand, the partitioning makes losses of instructions per clock cycle due to communication among register files. Not only the degree of partitioning, but the organization of partitioned register files also aects the access time of register files and the amount of inter-PE communication. In this paper, we investigate appropriate degrees of partitioning and organizations of partitioned register files in various 8-way issue clustered architectures. The results show that the eight single-issue PEs or the four double-issue PEs with the non-consistent register file organization can achieve the highest instructions per second and the speedup compared with the non-partitioned organization is 1.59 in the MediaBench suite and 1.69 in the SPEC2000int suite.