A PROPOSED CACHE LINE IMPLEMENTATION SOLUTION WITH ERROR/CORRECTING CAPABILITIES FOR MANAGING CACHE COHERENCY IN MULTIPROCESSOR SYSTEMS
Daniela Elena Popescu · 2009
The paper presents a solution for designing a cache coherency state machine for a multiprocessor system with error/correcting capabilities for the unidirectional errors and the used resources implied by a FPGA implementation of our solution. The cache coherency method used is based on the MESI protocol. The implementation is realized with FPGA by using the ALTERA Program.