Mixed Signal Verification of an FPGA-Embedded DDR3 SDRAM Memory Controller using ADMS
A. A. Zaliznyak, M. Kabani, John S. Lam, Chong Lee · 2007
System-level verification of a high-end FPGA with an embedded DDR3 SDRAM external memory controller presents challenges to designers that exceed those encountered in ASIC-like verification flows due to the mixed-signal nature of the design. The Stratix III FPGA with a DDR3 Hard IP is fabricated on a 65nm process. The memory interface is comprised of programmablewidth data groups running at 800-Mbps per data bit. The memory controller consists of custom/analog Hard IP (Read, Write, Command/Address paths and the Clock Management) and the Soft IP (Autocalibration IP and Memory Controller) and with the External Memory device model comprise a mixed-signal system. See Figure 1. Traditional Verilog verification methodology, while guaranteeing functional aspect of the verification flow, is not capable of verifying the adherence to the system-level timing specifications, nor in accurately predicting system timing budget. This paper describes a strategy devised and successfully utilized for the verification of the embedded DDR3 SDRAM external memory controller in the FPGA. The mixed-signal verification methodology is based on the use of Mentor Graphics ADMS mixed-mode simulator with the Mentor Graphics Fast SPICE engine ADiT enabled. It presents steps taken in the verification flow dealing with the simulation data preparation, the usage of the specific features of ADMS, and the verification process automation.