Some Aspects Of Dynamically Reconfigurable Circuits De- sign Methodology - Timing Constraint Tool
Piotr Amrozik, Andrzej Napieralski · 2010
This paper is devoted to a proposal of a dynami# cally reconfigurable circuits design methodology. Experience gained during the design of a bio# inspired dynamically reconfigurable chip for the European PERPLEXUS project [1], called Ubichip [2], is the main motivation to present the topic. During the design, an author’s project team en# countered a few major issues linked to Ubichip’s architecture and reconfigurability. Modularity and hierarchy of the chip can be numbered among first group. Among the second one, timing loops and timing constraining are the most challenging. It must be stressed that issues linked to the de# sign of the Ubichip can be directly applied to the other reconfigurable devices. Therefore, the Ubichip can be, and is treated as sample architecture for de# scribing design methodology dedicated for such a class of circuits. All of the issues mentioned above were solved exploiting available CAD tools and recommended design methodologies. But some of the problems, like timing constraining of dynamically reconfigur# able circuits are still not effectively supported by those standard methodologies. The author therefore have decided to propose a new tool which should be helpful during an early stage of the dynamically re# configurable circuit design.