Zynq-7000 All Programmable SoC Accelerator for Floating-Point Matrix Multiplication using Vivado HLS
Daniele Bagni, Juanjo Noguera, Fernando Martinez Vallina · 2013
This application note describes how to use Vivado® High Level Synthesis (HLS) to develop a floating-point matrix multiplication accelerator with an AXI4-Stream interface and connect it to the Accelerator Coherency Port (ACP) of the ARM CPU in the Zynq®-7000 All Programmable SoC. The floating-point matrix multiplication accelerator modeled in the C/C++ code can be quickly implemented and optimized into an RTL design using Vivado HLS. The solution is then exported as a pcore connected with an automatically created AXI4-Stream interface to the ACP of the Zynq-7000 AP SoC Programmable System (PS). The connection is made through a Direct Memory Access (DMA) core in the Programmable Logic (PL) of the Zynq-7000 device. Xilinx Platform Studio (XPS) is used to design the hardware of the Zynq-7000 AP SoC PL, including the matrix multiplier peripheral, the DMA engine and an AXI timer. The Software Development Kit (SDK) is used to design the software on the Zynq-7000 AP SoC PS to manage the peripherals.